Chopping is frequently used to eliminate amplifier offset. For example, switches at the input and output of a differential amplifier are operated to reverse the polarity of the offset error so that it appears at the output alternately as positive and negative offsets which are then filtered out to eliminate the offset from the primary signal. Chopping also addresses the 1/f flicker noise problem, which is becoming more of a problem in process geometries in the 0.25 micron range and lower, by transferring 1/f flicker noise to a higher frequency with the offset where it too can be filtered out.
One problem with chopping is that it introduces an input current which causes a reduction in input impedance. Further the input current increases with increasing chop rate. Chopping is often used with analog to digital circuits (ADC's) where the chopping rate is the sampling rate of the ADC. This high rate of chopping produces undesirably large input current and the sampling rate is normally desired to be high. In sigma delta (ΣΔ)converters the sampling rate is generally quite high, 100 KHz–10 MHz, but the output conversion rate can be much lower. For high resolution Σ Δ converters the over sampling rate can be 200 to 2000. Σ Δ converters often use a buffer amplifier input to increase the input impedance and chopping can be effected at that buffer amplifier to eliminate its own offset and 1/f flicker noise. Once the positive and negative offsets have been generated by chopping they can be combined or filtered either by the Σ Δ modulator in the Σ Δ converter or the digital filter in the Σ Δ converter or a subsequent filter. Normally a Σ Δ modulator receives two input samples per modulator cycle and the offset voltages can be inverted twice each cycle by chopping. Thus one input sample is proportional to (Vin+offset) the other (Vin−offset). The first integrator in the Σ Δ modulator sums those samples, that is, the offset voltages are sampled with the input voltage. The integrator thus combines the chopped inputs, cancels the offsets and outputs the sampled input. Another approach is to chop the input at the output conversion rate as disclosed in U.S. Pat. No. 5,675,334. In this approach one conversion includes a positive offset, the next a negative offset so that two full conversions are required to get an output with the offset cancelled.
It is possible to use the digital filter in the Σ Δ converter to remove the chopped offset as in Cirrus Logic's CS5531. In that approach the chop rate is lower than the input sampling rate but it is a fixed rate. The chopping rate then causes a fixed level of undesirable input current independent of output rate. Thus as you reduce the output rate to improve the resolution of the converter the input current and the resulting offset error do not reduce accordingly but remain fixed. Another shortcoming is that this approach only works with digital filters whose time domain response is symmetrical. Still another shortcoming is that the timing of the chopping is also critical: if is not done at the correct time the cancellation of the offset is not complete and an offset still appears at the output.